Immediate Interviews
Menlo Park, CA
Full Time
Responsibilities
•Drive the top-level Architecture definition and develop the necessary RTL
•Drive the chip-level integration, verification plan development and verification
•Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
•Contribute to ASIC digital Architecture, design and verification
•Support hand-off and integration of blocks into larger SOC environments
•Assist with performance/power analysis of IP models
Qualifications
•Contribute to scalable architecture and Architecture designs for low-power graphics IP design
•3+ years of experience as a Digital Design Engineer and/or a Chip Lead
•Experience in RTL coding, synthesis and/or SoC Integration
•Experience in digital design Architecture
•Experience with at least 1 procedural programming language (C, C++, Python etc.)
•Bachelor’s in Electrical Engineering/Computer Science or equivalent experience
